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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDHSR, External Debug Halting Syndrome Register</h1><p>The EDHSR characteristics are:</p><h2>Purpose</h2>
        <p>Holds syndrome information for a debug event.</p>
      <h2>Configuration</h2><p>EDHSR is in the Core power domain.
    </p><p>This register is present only when FEAT_EDHSR is implemented. Otherwise, direct accesses to EDHSR are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>EDHSR is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="23"><a href="#fieldset_0-63_41">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-40_40-1">GCS</a></td><td class="lr" colspan="8"><a href="#fieldset_0-39_24">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="8"><a href="#fieldset_0-39_24">RES0</a></td><td class="lr" colspan="6"><a href="#fieldset_0-23_18">WPT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17">WPTV</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16">WPF</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">FnP</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-13_13-1">VNCR</a></td><td class="lr" colspan="2"><a href="#fieldset_0-12_11">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-10_10">FnV</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8-1">CM</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6-1">WnR</a></td><td class="lr" colspan="6"><a href="#fieldset_0-5_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-63_41">Bits [63:41]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-40_40-1">GCS, bit [40]<span class="condition"><br/>When FEAT_GCS is implemented and FEAT_Debugv8p9 is implemented:
                        </span></h4><div class="field"><p>Guarded control stack data access.</p>
<p>Indicates that the Watchpoint debug event is due to a Guarded control stack data access.</p><table class="valuetable"><tr><th>GCS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The Watchpoint debug event is not due to a Guarded control stack data access.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The Watchpoint debug event is due to a Guarded control stack data access.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-40_40-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-39_24">Bits [39:24]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-23_18">WPT, bits [23:18]</h4><div class="field">
      <p>Watchpoint number. When EDHSR.WPTV is 1, holds the index of a watchpoint that triggered the Watchpoint debug event.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-17_17">WPTV, bit [17]</h4><div class="field">
      <p>Watchpoint number valid.</p>
    <table class="valuetable"><tr><th>WPTV</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>EDHSR.WPT field is not valid, and holds an <span class="arm-defined-word">UNKNOWN</span> value.</p>
        </td><td>When FEAT_Debugv8p9 is not implemented</td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EDHSR.WPT field is valid, and holds the number of a watchpoint that triggered the Watchpoint debug event.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-16_16">WPF, bit [16]</h4><div class="field">
      <p>Watchpoint match might be False.</p>
    <table class="valuetable"><tr><th>WPF</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The watchpoint matched the original access or set of contiguous accesses.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The watchpoint matched an access or set of contiguous accesses where the lowest accessed address was rounded down to the nearest multiple of 16 bytes and the highest accessed address was rounded up to the nearest multiple of 16 bytes minus 1, but the watchpoint might not have matched the original address of the access or set of contiguous accesses.</p>
        </td><td>When FEAT_SME is implemented or FEAT_SVE is implemented</td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_15">FnP, bit [15]</h4><div class="field">
      <p><a href="ext-edwar.html">EDWAR</a> not Precise.</p>
    <table class="valuetable"><tr><th>FnP</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>If the <a href="ext-edwar.html">EDWAR</a> is valid, it holds the virtual address of an access or sequence of contiguous accesses that triggered the Watchpoint debug event.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>If the <a href="ext-edwar.html">EDWAR</a> is valid, it holds any virtual address within the smallest implemented translation granule that contains the virtual address of an access or set of contiguous accesses that triggered the Watchpoint debug event.</p>
        </td><td>When FEAT_SME is implemented or FEAT_SVE is implemented</td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-14_14">Bit [14]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-13_13-1">VNCR, bit [13]<span class="condition"><br/>When FEAT_Debugv8p9 is implemented:
                        </span></h4><div class="field">
      <p><a href="AArch64-vncr_el2.html">VNCR_EL2</a> access. Indicates that the Watchpoint debug event came from use of <a href="AArch64-vncr_el2.html">VNCR_EL2</a> register by EL1 code.</p>
    <table class="valuetable"><tr><th>VNCR</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The Watchpoint debug event was not generated by the use of <a href="AArch64-vncr_el2.html">VNCR_EL2</a> by EL1 code.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The Watchpoint debug event was generated by the use of <a href="AArch64-vncr_el2.html">VNCR_EL2</a> by EL1 code.</p>
        </td><td>When FEAT_NV2 is implemented</td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-13_13-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_11">Bits [12:11]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-10_10">FnV, bit [10]</h4><div class="field">
      <p><a href="ext-edwar.html">EDWAR</a> not Valid.</p>
    <table class="valuetable"><tr><th>FnV</th><th>Meaning</th><th>Applies when</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-edwar.html">EDWAR</a> is valid.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-edwar.html">EDWAR</a> is not valid, and holds an <span class="arm-defined-word">UNKNOWN</span> value.</p>
        </td><td>When FEAT_SME is implemented or FEAT_SVE is implemented</td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-9_9">Bit [9]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-8_8-1">CM, bit [8]<span class="condition"><br/>When FEAT_Debugv8p9 is implemented:
                        </span></h4><div class="field">
      <p>Cache maintenance. Indicates whether the Watchpoint debug event came from a cache maintenance instruction.</p>
    <table class="valuetable"><tr><th>CM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The Watchpoint debug event was not generated by the execution of one of the System instructions identified in the description of value 1.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The Watchpoint debug event was generated by the execution of a cache maintenance instruction. The <a href="AArch64-dc-zva.html">DC ZVA</a>, <a href="AArch64-dc-gva.html">DC GVA</a>, and <a href="AArch64-dc-gzva.html">DC GZVA</a> instructions are not cache maintenance instructions, and therefore do not cause this field to be set to 1.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_8-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_7">Bit [7]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-6_6-1">WnR, bit [6]<span class="condition"><br/>When FEAT_Debugv8p9 is implemented:
                        </span></h4><div class="field">
      <p>Write not Read. Indicates whether the Watchpoint debug event was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.</p>
    <table class="valuetable"><tr><th>WnR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Watchpoint debug event caused by an instruction reading from a memory location.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Watchpoint debug event caused by an instruction writing to a memory location.</p>
        </td></tr></table><p>For Watchpoint debug events on cache maintenance instructions, this field is set to 1.</p>
<p>For Watchpoint debug events from an atomic instruction, this field is set to 0 if a read of the location would have generated the Watchpoint debug event, otherwise it is set to 1.</p>
<p>If multiple watchpoints match on the same access, it is <span class="arm-defined-word">UNPREDICTABLE</span> which watchpoint generates the Watchpoint debug event.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-6_6-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-5_0">Bits [5:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h2>Accessing EDHSR</h2><h4>EDHSR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>Debug</td><td><span class="hexnumber">0x038</span></td><td>EDHSR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When DoubleLockStatus(), or !IsCorePowered() or OSLockStatus(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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